Study of Matching Properties of Graded-Channel SOI MOSFETs

The concept of matched devices is one of the most important features in analog circuit design, as most analog circuits operation rely on the similarity of electrical behavior of close devices [1]. However, in practice, the characteristics of designed matched transistors are slightly different. Therefore, the design of precise analog circuits requires studies into the matching behavior of devices in order to yield a good understanding of the physical phenomena of device variations and its impact on the circuit performance. The Graded-Channel (GC) SOI nMOSFET is a device with asymmetric doping channel profile, proposed to improve the SOI analog characteristics [2]. By simply using a mask arrangement in the standard SOI CMOS process, the threshold voltage ion implantation is performed at the source side only, keeping the remaining channel, at the drain side, with the natural wafer doping concentration. This so-called lightly doped region presents negative threshold voltage and, in a simplistic way, can be understood as an extension of the drain region for positive values of applied front gate voltage (VGF), reducing the effective channel length (Leff = L – LLD, L being the mask channel length and LLD is the length of the lightly doped region). Figure 1 presents the cross section of a GC SOI nMOSFET. Previous works reported several GC devices advantages over conventional ones for analog applications [2, 3, 4], namely larger transconductance (gm), reduced drain output conductance (gD) and appreciable reduction in the harmonic distortion [5], as already demonstrated in analog circuits such as operational transconductance amplifiers [6] and current mirrors [7]. Despite the advantages of this transistor for analog applications, few information of matching properties of GC SOI transistors is known [8]. In this work an overall evaluation of the impact of the GC channel engineering on the matching properties of SOI transistor will be presented.